1. Field of the Invention
This invention relates to multiprocessing systems and more particularly to apparatus for providing communication between processors in such a system.
2. Description of the Prior Art
In a multiprocessing system wherein several processors share a common memory, numerous concurrent functions or tasks may be multiplexed by the processors. Facilities must be provided for insuring necessary isolation and communication between tasks, and for assigning available processors to tasks which are ready to be executed.
In addition, a mechanism must be provided by which processors can signal each other. For example, a processor must be able to signal an idle processor that a task has become available for execution.
A number of techniques have been employed in the past to perform this communication function. The following summary of prior patents illustrates the current state of the art.
In Belt etal U.S. Pat. No. 3,541,517 communication between processors in a multiprocessing system is handled by a central controller which is coupled to communicate with all the processors and with a shared memory. The central controller has a "communication set" in memory which identifies a particular program to be executed. The controller then notifies one of the processors to execute the program. When a processor reaches a point where it is free, it fetches the communication set, and using the parameters therein gets and executes the program.
Driscoll U.S. Pat. No. 3,551,892 utilizes the central timer locations set aside for each processor. The timer locations are extended in size so that the system control software can leave messages to a potential recipient in the special storage area, one for each processor, adjacent the processor's central timing location. A send message instruction executed by a sending processor locates the special storage therein. At fixed times during the operational cycle of each processor the processor accesses the storage at the special storage location assigned to it to see if any messages are present. If a message is present the processor fetches the message and performs the task associated therewith. This system relies on a supervisory program and on the IBM system 360 condition code mechanism to provide software control for synchronizing the processors. For example the system 360 test and set instruction provides the interlock for two processors competing for the same message storage location. This patent provides for communication to a specific processor.
Barner U.S. Pat. No. 3,771,137 is an example of a broadcast type of system. A number of processors are each equipped with a buffer memory. A broadcast system allows any processor to query via a memory control all other processors to determine whether desired data is in one of the other processor's buffer. If the data is present in one of the other processor's buffer, memory control transfers the data to main memory to update the copy in memory (a read cycle followed by a write cycle). This patent discloses means for communication with all other processors in the system to control memory access in a buffer/backing store memory heirarchy.
In Moore U.S. Pat. No. 3,778,780 a priviledged instruction, signal processor, is utilized to initiate communication between processors. This is accomplished by means of an operation request block (ORB) which contains parameters identifing a task. Only one ORB is provided in the system. An ORB pointer is passed from a sending unit (SU) to a receiving unit (RU). The ORB storage space is prepared by supervisory programming in the SU and contains the task pointer. The RU fetches the ORB, performs the task, then posts an interrupt to the SU. When SU honors the interrupt, it gets the ORB pointer from the RU. The SU in the supervisory state examines the ORB space and uses the task pointer to resume problem state execution.
The ORB concept is implemented in an operating system type of computer environment and utilizes priority interruption of the initiating unit in order to complete the transfer of intelligence via the communication mechanism.
In Bergh etal U.S. Pat. No. 3,820,079 the communication mechanism is distributed throughout the system. Each module in the system is provided with a Modular Control Unit (MCU) which controls the interface between modules. Any module can request information from any other module by manipulating registers and utilizing buffers in each MCU to retain control information concerning data transfers.
In Gray U.S. Pat. No. 3,833,889 communication between processors is accomplished by a dedicated hardware buffer, an interlock register, which handles the transfer of data without the data going through memory. It also communicates completion of a process when two or more processors are operating on the same problem. Data can also be transfered through the memory, in which case a flag is set in the interlock register which is then interrogated by the recipient processor when it is to accept the data. Special purpose hardware moves data in and out of the interlock register.
None of the prior techniques for interprocessor communication provide facilities for system-wide communication as well as processor specific communication, which facilities can be accessed by either system hardware or system software.
It is therefore a primary object of this invention to provide an interprocessor communication system which handles both system-wide as well as processor specific communication.
A further object of this invention is to provide an interprocessor communication mechanism that is hardware recognized and therefore does not require software control programming.
Another object of this invention is to provide means for locking a communication mechanism when a message is sent, and clearing the mechanism when all intended recipient processors have responded.
A further object of this invention is to provide means for enabling software to access the interprocessor communication mechanism.
A further object of the invention is to provide a mechanism for broadcasting a message to many processors, which mechanism has controls for ensuring that all processors have responded before allowing any more messages to be sent.